1. Field of the Invention
The present invention relates to a semiconductor device with an MIM (Metal Insulating Metal) capacitor, and a process for manufacturing the semiconductor device.
2. Description of the Related Art
Semiconductor devices provided with Cu wiring of a damascene structure and MIM capacitors are now available.
FIG. 28 is a sectional view of a conventional semiconductor device. As shown in FIG. 28, a via hole 43 and a wire 44, which are made of, for example, Cu, are provided in a film 41 of a low dielectric constant and a film 42 of a high dielectric constant. A Cu-diffusion-preventing film 45 is provided on the high dielectric film 42 and wire 44, and a capacitor 49 is provided on a selected portion of the Cu-diffusion-preventing film 45. The capacitor 49 is formed of a lower electrode 46, a dielectric film 47 and an upper electrode 48. An insulating film 50 is provided on the capacitor 49 and Cu-diffusion-preventing film 45. The surface of the insulating film is flattened by CMP (Chemical Mechanical Polishing).
In such conventional semiconductor devices, it is desirable that the insulating film 50 be formed of a low dielectric film in order to reduce the parasitic capacitance between wires.
However, since the low dielectric film is a rough film, a crack may occur if the surface of the film is flattened. Therefore, it is very difficult to level, by CMP, the surface of an insulating film 50 formed of a low dielectric film. To avoid this, a high dielectric film could be used as the insulating film 50, as thus would reduce the formation of cracks under CMP.
However, since the capacitor 49 is provided on a selected portion of the Cu-diffusion-preventing film 45, there is a step corresponding to the thickness of the capacitor 49 between the area provided with the capacitor and the area without. To eliminate the step caused by the presence of the capacitor 49, it is necessary to form an insulating film 50 in the area with no capacitor on the Cu-diffusion-preventing film 45. Thus, as stated above, a high dielectric film or insulating film 50 is provided on the film 45 to surround the capacitor 49. The provision of the high dielectric insulating film 50 to fill the step caused by the capacitor 49 inevitably increases the parasitic capacitance between wiring layers.
As described above, in the conventional semiconductor device, it is very difficult to level the surface of the insulating film 50 by CMP.